The subject invention pertains to microprocessors, and particularly microprocessors used in signal processing where operations must be performed in real time at tremendously high rates, on the order of millions of operations per second. The subject invention pertains to a microprocessor architecture method and apparatus for operating at rates over two million operations per second.
A microprocessor configured according to the preferred embodiment employs two instructions types: those which do and those which do not require external memory fetch. Those instructions requiring no external memory fetch will be referred to as Type I instructions, while those requiring data to be fetched from external memory will be referred to as Type II instructions. Generally, Type II instructions are comprised of two parts: one part being the Operand-Fetch rule, the other being the Operation rule. A verbalization of a Type I instruction might be, for example, "Complement the Accumulator," while a verbalization of a Type II instruction might be, for example, "Fetch the contents of memory being pointed to by index register R.sub.3 and add this number to the accumulator."
As alluded to, a very important measure of microprocessor performance, especially for signal processors, is the number of operations per second that can be performed. In order to maximize the number of operations per second, it is desirable to achieve maximum exploitation of each clock cycle as microprocessor operation. A well-known technique for more efficiently using each microprocessor cycle is so-called "pipelining" whereby one or more subsequent instructions are fetched before the execution of the first is completed.
It is also desirable to use few buses in the microprocessor architecture in order to reduce the number of input-output pins, simplify external memory and allow a von Neumann architecture wherein instruction and data memory may share the same devices.
The subject invention finds particular application in a microprocessor employing Type I and Type II instructions, pipelining and two buses--an address bus and instruction-data bus. In such a machine, the different types of instructions and delays involved lead to difficulties with organization of processing operations and thus to resultant waste of precious computing time, detracting from the number of operations per second which can be accomplished.